The present invention relates generally to semiconductor inspection and defect analysis techniques, and more specifically to techniques for setting up the inspection and defect analysis apparatus.
Generally, the industry of semiconductor manufacturing involves highly complex techniques for fabricating integrating circuits using semiconductor materials. Due to the large scale of circuit integration and the decreasing size of semiconductor devices, the semiconductor manufacturing process is prone to processing defects. Testing procedures are therefore critical to maintain quality control. Since the testing procedures are an integral and significant part of the manufacturing process, the semiconductor industry is constantly seeking for more accurate and efficient testing procedures.
Typical inspection processes detect defects by comparing similar semiconductor device areas on a wafer. The differences detected between the two device areas can either be a defect, which can cause a device to function improperly, or a nuisance, which will not affect system operations. An integral phase of semiconductor wafer inspection involves optimizing the settings, commonly referred to as the “recipe,” of an inspection device so that it can accurately distinguish defects from nuisances.
After potential defects are found by an inspection system, the wafer is typically transferred to a review tool for classification of the defects. However, classification of the defects requires optimizing the settings of the review tool, also referred to as a “recipe”, so that the review tool can adequately classify the potential defects or determine that the potential defects are nuisances or false defects.
In sum, analysis of the defects on a particular wafer lot requires setting up and optimizing a recipe for an inspection tool and setting up a different recipe for the review tool. Setting up two recipe for two different tools is time consuming and complex. Additionally, conventional inspection and review tools typically require batch type processing of and entire cassette of wafers. That is, a cassette is first loaded into the inspection tool for localization of potential defects. After the entire cassette is inspected, the entire cassette is then loaded into the review tool for defect analysis. This batch type processing prevent the full adoption of true in-line monitoring of the manufacturing process. For example, adjustment of the defect inspection and sampling process based on information gained from defect review within a same lot is impossible in conventional testing systems.
Thus, improved apparatus and techniques for analyzing defects are needed. More specifically, techniques and apparatus for efficiently setting up recipes for such apparatus are required.